For mature semiconductor products in high-volume manufacture, a considerable effort is made to determine and eliminate the predominant failure mechanisms identified in the initial reliability studies so that the normal life failure rate of device meets or exceeds the design goal. Possible wear-out mechanisms will have been identified and eliminated, either through modifications in the process or in the design. However, the manufactured devices will normally show the existence of continuing early life failures or infant mortality failures. Example of such defects includes oxide pinholes, photoresist or etching defects resulting in near-opens or shorts, contamination on the chip or in the package. A number of stress tests have thus been developed to accelerate the effects of various failure mechanisms.
A burn-in test, which is one of such stress tests, is typically performed before or after packaging (encapsulating) of a semiconductor device, in order to test the reliability of its internal circuits therein. The purpose of the burn-in test is to operate semiconductor memory devices for some period of time during which most of the devices that are subject to infant mortality failure actually fail. Failing the burn-in testing is preferable to having devices fail after they are installed in a system and delivered to the customer. The conditions during burn-in presumably accelerate the failure mechanisms that contributed to the infant mortality failures.
For many years, the demand for unencapsulated semiconductor dies (sometimes referred to as "Known Good Die"), which are typically manufactured in wafer form, has been rapidly increasing, because of assembly flexibility along with relatively low die prices. Burn-in tests of bare die (i.e., wafer burn-in test) have actually been carried out in the semiconductor industry and further advances for performing more effective wafer burn-in tests have been made.
During a wafer burn-in test for a semiconductor memory device such as a dynamic random access memory or a static random access memory, in order to detect defects or strength of memory cells stored in the same device, a plurality of word lines are selected at a time and an exterior voltage higher than the supply voltage is applied to each of the selected memory cells, thereby checking whether the memory cells are in good state or in bad state.
FIG. 1 is a schematic circuit diagram of a conventional static random access memory device. Referring to FIG. 1, the static random access memory (hereinafter, referred to as SRAM) includes an array 100 of memory cells located in a matrix of rows and columns, bit lines BLi and (where, i=1 to m), word lines WLj (where, j=1 to n), and bit line precharge circuits 200.sub.-- 1 to 200.sub.-- m. A pair of bit lines and a word line correspond to each memory cell. Each of the bit line precharge circuits 200.sub.-- i (i=1 to m) includes two transistors T1 and T2 and selectively delivers current to corresponding a bit line pair during normal and test modes in response to control signals PBL1 and PBL2.
FIG. 2 is a schematic circuit diagram of a typical six transistor CMOS SRAM cell with a corresponding bit line precharge circuit. The six transistor cell of FIG. 2 is capable of storing one binary bit of information. Referring to FIG. 2, the shown memory cell includes a bistable circuit composed of transistors T3, T4, T5, and T6. The memory cell further contains access transistors T7 and T8 serving as switches each of which being coupled between the bistable circuit and corresponding bit line BLi or 0.
In a wafer burn-in test mode, as well known, an appropriate number of word lines are selected at a time and all the memory cells coupled to the selected word lines are stressed by repeatedly performing write and read operations on those word lines. When the memory cell is addressed, that is, when an enable signal is placed on the word line WLj, transistors T7 and T8 become conductive. Therefore, bit line BLi becomes 788787 coupled to the drains of transistors T3 and T5 and the gates of transistors T4 and T6, and bit line 0 becomes coupled to the gates of transistors T3 and T5 and the drains of transistors T4 and T6. In the case of a data write operation, data writing of the cell is performed by means of the bit line precharge circuit 200.sub.-- i, and bit lines BLi and 0 are placed in complementary states by the bit line precharge circuit 200.sub.-- i. Therefore, in this mode, one bit data is stored as voltage levels with the two sides (i.e., nodes A and B) of the bistable circuit (T3, T4, T5, and T6) in opposite voltage configurations.
For convenience of explanation, assume that control signal PBL1 is activated and control signal PBL2 is inactivated when data of logic `1` state is written into the memory cell, and the control signal PBL1 is inactivated and the control signal PBL2 is activated when data of logic `0` state is written. In a write operation of logic `1` data, transistors T1, T7, and T8 are rendered conductive, while transistor T2 is rendered non-conductive. Bit line BLi and node A, thus, go high so that transistor T4 becomes conductive but transistor T6 becomes non-conductive. As a result, node B goes low. In response to the voltage level of node B, transistor T5 becomes conductive but transistor T3 becomes non-conductive. Thus, node A goes high. To the contrary, in the case of logic `0` data write operation, transistors T2, T7, and T8 become conductive, while transistor T1 becomes non-conductive. Bit line 0 and node B then go high, so that transistor T5 becomes non-conductive but transistor T3 becomes conductive. As a result, node A goes low. In response to the voltage level of node A, transistor T3 is turned off but transistor T5 is turned on, so that node B goes high.
Generally, each transistor within bit line precharge circuits should be designed to have an appropriate current driving ability, that is, only enough to supply current necessary for normal operation mode in which one word line is selected, considering chip size, power consumption in normal operation, etc. However, during a write/read operation of wafer burn-in test mode, since a plurality of word lines are simultaneously selected unlike during normal operation mode, there may be a shortage of cell current to the individual cells coupled to the selected word lines. This is due to the limitation of current driving ability of transistors within bit line precharge circuits. The cell current shortage will result in burn-in test instability and test failure at worst.
Moreover, this cell current shortage also makes it difficult to change the data states of the latched storage cells. For instance, in case that nodes A and B of FIG. 2 are retained low and high, respectively (i.e., logic `0` data is stored in the cell), when a logic `1` data write operation begins, transistors T1 and T7 are driven conductive and thus cell current flows from transistor T1 through transistors T7 to node A. However, since transistor T3 still remains conductive during early burn-in write operation, the cell current sinks into ground line 2. This cell current sink may be more serious in a six transistor full CMOS type cell than in other types. Therefore, in order to supply enough cell current in write operation of burn-in test mode, it will be required to increase the size of bit line precharge transistors, resulting in increasing of chip size and power consumption in normal operation mode.